UC Davis

In this dissertation, a general embedding is proposed to boost the power gain of any deviceto the maximum achievable gain (Gmax), which is defned as the maximum theoretical gain of the device. Using a gain-plane based analysis, two linear-lossless-reciprocal embeddings are used to perform a movement from the coordinate of the transistor to the coordinate that corresponds to Gmax. The proposed embedding is applied to a 10um common-source NMOS transistor, and the theoretical and simulation results are presented and compared. The prop- erties of the embedded transistor are inspected, and the few issues in implementation are investigated and addressed. Using the proposed general embedding, an amplifer is imple- mented in a 65nm CMOS process with a measured power gain of 9.2dB at 260GHz, which is the highest frequency reported in any silicon-based amplifer. Then, the effect of gain and embedding of amplifying cells (amp-cell) on the output power of power amplifers at high mm-wave and terahertz frequencies is studied. These are the frequency bands where match- ing loss becomes comparable to the gain of the amp-cell in most solid-state technologies. By deriving power equations of embedded amp-cell, power contours are plotted in the gain-plane and an optimum embedding is designed to maximize the output power for a desired gain. To showcase the theory, a high-frequency, high-power amp-cell, called matched-cascode, is introduced, and afterwards embedded to boost both power gain and output power. To in- crease the output power even further, a differential slot power combiner is introduced and its equivalent circuit is analyzed. Finally, using the embedded matched-cascode cell, and the slot power combiner, a 28 power amplier is implemented in 65nm Bulk CMOS. The PA features a Psat, and OP1dB of 9.4dBm and 6.3dBm, respectively, at 200GHz, and a maximum power gain of 19.5dB.